The present invention relates in particular to digital image processing systems and methods for efficiently scaling digital images.
Processing of digital images typically follows a rasterized path. Pixel values are read and processed from left to right within a single line, and lines are processed from top to bottom. Image processing operations such as scaling operate on areas that span multiple lines and columns of a digital image. Typically, to scale a group of image pixels, line buffering is necessary to temporarily store pixel values for multiple lines. Even though an area-based algorithm may only use a small number of pixels within a given line, the entire line must be buffered before scaling operations on the columns may be performed. Storage allocation for the multiple lines of scaled output data may be static or dynamic. The allocation size is dependent on the scale factor, the pixel resolution per area, the image size and the column length. Because memory resources are limited, efficient static memory allocation is preferred.
When a scaling operation is implemented in hardware, the resolution and image width will define the amount of memory, typically SRAM, needed for buffering. If the resolution doubles, the amount of memory doubles. Typically the amount of SRAM available for buffering is fixed within an Application Specific Integrated Circuit (ASIC) implementing the desired function. Thus, a decision regarding the size of the buffer must be made early on in a design project in which line buffering will be required. If a later product needs more buffering, or if specifications change, the ASIC must be re-designed. This can add significant cost and delay to the project.